[Tutorial] Productive Parallel Programming for FPGA with High Level Synthesis

Torsten Hoefler and Johannes de Fine Licht demonstrate how to use high-level synthesis to achieve scalable pipeline parallelism on FPGAs.

Speakers: Torsten Hoefler, Johannes de Fine Licht Venue: SC'20 Abstract: Energy efficiency has become a first class citizen in the design of large computing systems. While GPUs and custom processors show merit in this regard, reconfigurable architectures, such as FPGAs, promise another major improvement in energy efficiency, constituting a middle ground between fixed hardware architectures and custom-built ASICs. This tutorial shows how high-level synthesis (HLS) can be harnessed to productively achieve scalable pipeline parallelism on FPGAs. Attendees will learn how to target FPGA resources from high-level C++ or OpenCL code, guiding the mapping from imperative code to hardware, enabling them to develop massively parallel designs. We treat well-known examples from the software world, relating traditional code optimizations to hardware, building on existing knowledge when introducing new topics. By bridging the gap between software and hardware optimization, our tutorial aims to enable developers from a large set of backgrounds to start tapping into the potential of FPGAs for high performance codes. Find all the tutorial material on our website: spcl.inf.ethz.ch/Teaching/hls-tutorial/ Learn more about FPGA optimizations: arxiv.org/abs/1805.08288 The demonstrated code is available at: github.com/spcl/hls_tutorial_examples Part 0 (Introduction): 0:00 Part 1 (Practical): 22:22 - Example 0: 49:41 - Example 1: 1:09:30 - Example 2: 1:24:50 - Example 3: 1:39:08 - Example 4: 1:59:39 - Example 5: 2:24:49 - Example 6: 2:43:40 - Example 7: 2:57:36