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ASPLOS Keynote: The Golden Age of Compiler Design in an Era of HW/SW Co-design by Dr. Chris Lattner

SiFive

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  • Presented by Dr. Chris Lattner
  • An opinion. It argues one side of a question engineers disagree on.

Advanced. Deep dive for people who know the field.

51K views5 years ago7 recommendations

Systems programmingHardwareCompilers and interpretersCPUs and computer architecturePerformance and optimization

Chris Lattner discusses the need for unified compiler infrastructure like MLIR and CIRCT to support modern hardware accelerators.

This week at the ASPLOS 2021 conference, Dr. Chris Lattner gave the keynote address to open the event with a discussion of the Golden Age of Compilers in an era of hardware and software co-design. ASPLOS is a multi-disciplinary conference for research that spans the boundaries of hardware, computer architecture, compilers, languages, operating systems, networking, and applications. ASPLOS provides a high-quality forum for scientists and engineers to present their latest research findings in these rapidly changing fields. It has captured some of the major computer systems innovations of the past two decades (e.g., RISC and VLIW processors, small and large-scale multiprocessors, clusters and networks-of-workstations, optimizing compilers, RAID, and network-storage system designs). This conference occurs at a time when computer architecture is facing great challenges, due both to the end of single-processor performance scaling and to new demands imposed by mobile and Giga scale computing. Chris Lattner co-founded the LLVM Compiler infrastructure project, the Clang compiler, the Swift programming language, the MLIR compiler infrastructure, the CIRCT project, and has contributed to many other commercial and open-source projects at Apple and Google. He now leads the Engineering and Product teams at SiFive. In this talk, Dr. Lattner will 'nerd out' on compilers, accelerators, and the "end of Moore's Law."

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7 people recommend this

What people say. Highly recommended as a visionary keynote on the future of compilers, hardware description languages, and MLIR.

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The Golden Age of Compiler Design in an Era of HW/SW Co-design by Dr. Chris Lattner

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ASPLOS Keynote: The Golden Age of Compiler Design in an Era of HW/SW Co-design by Dr. Chris Lattner

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The Golden Age of Compiler Design in an Era of HW/SW Co-design

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On “Cerebras’ new monster AI chip adds 1.4T transistors”

You might like this talk that describes parts of the compiler ecosystem that are lacking standardization for accelerators link to this video

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On ““Shared libraries are not a good thing in general””

They've tried variations of this. It takes instruction bits to describe these registers: 32 regs is 5 bits, target + src1 + src2 is 15 bits already. They've tried scratch pads. The Mill CPU's Belt is yet another approach. link link How to Use 1000 Registers link 1000 registers would be 10 bits. So they tried register windows. These are all good ideas but they get to compete. So far, I'm a huge AArch64 fan but I now see the purpose of RISC-V. I watched Chris Lattner's ASPLOS talk and it finally clicked. link to this video

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On “Chisel/FIRRTL Hardware Compiler Framework”

…w thread, I see familiar faces that are now actively contributing to CIRCT. There are mentions of many different hardware IRs in some of the posts, but at least three have first-class support in CIRCT today: FIRRTL3, LLHD4, and Calyx5. This is all very recent and experimental, but I would say the results are already promising. 1 link 2 link to this video 3 link 4 link 5…