Eric Bogatin explains the physics and practical guidelines for choosing and placing decoupling capacitors on a PCB to maintain signal integrity.
Practical examples to show what decoupling capacitors do. Explained by Eric Bogatin. Thank you Eric.
Links:
- Bogatin's Practical Guide to Prototype Breadboard and PCB Design: amazon.com/Bogatins-Practical-Prototype-Breadboard-Design/dp…
- The Myth of Three Capacitor Values: signalintegrityjournal.com/articles/1589-the-myth-of-three-c…
- Signal Integrity Academy (use FEDSI - 3 months free): bethesignal.com/bogatin/3monthsubscription.php
- FEDEVEL courses: courses.fedevel.com/
Chapters:
What is this video about
The schematic
The board / circuit
Example: Long rise time
2us rise time, no decoupling capacitor
Fast rise time, no decoupling cap
Fast rise time, moving probe
Estimating decoupling capacitor value
1000uF close to circuit
1000uF far from the circuit
1uF close to the circuit
Where to place decoupling capacitor
1 vs 2 capacitors
Sometimes more is better
Conclusion
Why 100nF capacitor?
Why PDN Graph?
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Why it's here
1 person recommends this
What people say. Recommended as an excellent resource for understanding how to properly size and place decoupling capacitors to minimize rail drop.
q
u/quirkyPillagerin r/embedded • Recommends
On “Isn't 1 decoupling cap per pin enough? Almost all designs for this IC use 2 per, their boards have double sided assembly but mine isn't - I don't have space.”
Benki spot on with the advice.
I have been doing the same and all my designs work well (minimal rail drop).
I started doing this after watching link to this video