The Mill CPU Architecture – The Compiler (10 of 13)

This lecture explains the Mill CPU's compiler toolchain, focusing on VLIW scheduling, latency passes, and targeting family members.

Please share via this link: MillComputing.com/docs/compiler 0:00:00 00 intro 0:02:05 04 Mill family 0:04:20 06 Late binding to family member 0:07:17 06 The Specializer 0:07:33 07 Specializer inputs – family member specification 0:11:09 08 Specializer inputs – code 0:13:12 09 Substitution pass 0:15:56 10 Wide issue 0:17:25 11 Exposed pipeline 0:19:15 12 Producers near consumers 0:19:58 14 Latency pass 0:24:20 15 Dependency count pass 0:25:27 16 Schedule pass 0:30:36 22 Placement pass 0:37:24 28 Symex pass (preview) 0:38:19 29 The Belt (review of earlier talk) 0:42:53 35 Symex pass, 1 0:55:13 43 Us it or lose it 0:56:17 44 The scratchpad 1:00:32 45 Symex pass, 2 1:03:14 47 The load problem 1:04:06 48 Every CPU’s goal – hide memory latency 1:05:57 49 Mill “deferred loads” 1:24:12 58 Questions 1:25:15 How is the belt implemented in hardware? 1:34:02 How does family member belt size affect performance? 1:37:27 How does the scheduling compare to optimal? 1:39:38 How does the delay argument to load work? 1:37:27 How does the scheduling compare to optimal? 1:41:10 What happens when overwriting an output register? 1:43:20 What happens on the belt for a function call? 1:46:29 How does the Mill do stackless Python or coroutines? 1:48:07 How does the belt not run out of frame numbers? 1:43:20 What happens on the belt for a function call? 1:51:05 Number of gates comparable to a DSP 1:57:47 Any plans for an FPGA? 1:58:21 The investor mailing list 1:58:51 We are a sweat-equity operation.