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Xilinx ILA Demo using Vivado 2020, Vitis, and Avnet Minized rev1

Robert Swan

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YouTube
  • Recommended by 2 people: 2 in engineering communities.
  • Presented by Robert Swan
  • May be out of date. The tools, versions or practices it shows have likely moved on.

Intermediate. Assumes working knowledge.

11K views6 years ago2 recommendations

HardwareTools and practiceEmbedded systemsDebugging

Robert Swan demonstrates how to use the Xilinx Integrated Logic Analyzer to monitor an eight-bit counter on an Avnet Minized board.

Walk through of developing a Zynq based design using ILA to monitor the output of an 8 bit counter.

Why it's here

2 people recommend this

What people say. Recommended as a helpful tutorial for setting up and using the Xilinx Integrated Logic Analyzer in Vivado and Vitis.

u/Typical-Cranberry120in r/FPGA • Recommends

very nice example YouTube Xilinx ILA Demo using Vivado 2020, Vitis, and Avnet Minized rev1
18View on Reddit

u/Ok_Measurement1399in r/FPGA • Recommends

Best Method for using Vivado ILA Hello, I'm new to using the Integrated Logic Analyzer in Vivado. I have found three videos that show how to do it. [video \^ here is a really easy way but it creates multiple ILA cores [video \^ this one you much place code in your HDL [video Which method do you like? Can you share any pros or cons? I have found that I must always load the .xlt file in order to get my probes to show up in the waveform window. Thank you
2View on Reddit

u/autocorrectsin r/FPGA • Mentions

ILA Core Clocking Hey guys, quick question for those that have used the ILA core in Vivado and have driven it using Vitis by arming the PS core (such as in this tutorial here: link to this video Also, Im posting here because I cannot for the life of me find the same question on Xilinx forums. My system tests signals as they come out of the RF Data Converter IP as I am doing some signal processing experiments and flash back and forth between the DACs and ADCs (running this experiment on RFSoC 4x2). One of my ILA cores is hooked up to an ADC clock from the RFDC that I run through a clocking wizard to x2 the clock to near 500 MHz, but whenever I run that ILA in the hardware manager I get the following…
2View on Reddit