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Tuesday @ 1130 ISA Shootout – a Comparison of RISC V, ARM, and x86 Chris Celio, UC Berkeley V2

RISC-V International

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  • Recommended by 2 people: 2 on Hacker News.
  • A classic. People kept recommending it from 2016 to 2020.
  • Presented by Chris Celio, UC Berkeley

Intermediate. Assumes working knowledge.

50K views10 years ago2 recommendations

Systems programmingHardwareCPUs and computer architecturePerformance and optimization

Chris Celio compares RISC-V, ARM, and x86 instruction set architectures using quantitative data on instruction counts and code density.

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2 people recommend this

What people say. Recommended for its quantitative comparison of code density and instruction counts across RISC-V, ARM, and x86 architectures.

legulereon Hacker News • Recommends

On “Intel Licenses ARM Technology to Boost Foundry Business”

> If you look at functionality per instruction byte, RISC is fairly low. You should watch this video: link to this video The most important information therein is that the difference in code density is minuscule between x86, ARM and RISC-V. The differences between GCC versions is even bigger. > The equations that you have to resolve to issue an X86 instruction are simply more complex than for ARM, and all that bit-flipping consumes power. It's actually just 3-10% of power consumption 1 and I even heard it claimed that the instruction decoding on ARM is larger than x86 1 link
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dkjaudyeqooeon Hacker News • Recommends

On “Apple M1 foreshadows Rise of RISC-V”

At best, that's a simplistic and misleading view, see the following talk for an in depth analysis: "Comparison of RISC V, ARM, and x86" link to this video
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u/Yoghurt42in r/compsci • Mentions

On “What are the alternatives to ARM?”

RISC-V, although it's only the ISA that's "open source", and implementers are allowed to extend the instruction set with proprietary opcodes; also they don't have to make their chip design open source (but there probably are/will be some open source chips designs). But anybody can make a RISC-V processor that will run every program that doesn't use proprietary opcodes; many vendors support it (NVidia for example), and "a lot" of work and research is being done on RISC-V. And apparently, [RISC-V performance in both speed and instruction size could become competitive with ARM and x64] OpenSPARC is probably closest to true open source chip, but AFAIK it's pretty much dead. BTW, ARMv2 (the one…
40View on Reddit

rwmjon Hacker News • Mentions

On “Ask HN: What's the value proposition of RISC-V?”

RISC-V has a compressed extension that compares favourably to even x86. See link to this video (bottom of the slide).
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nickikon Hacker News • Mentions

On “Boom v2: Open-source out-of-order RISC-V core [video]”

> because it turns out that getting high performance from an ISA with only simple and relatively large instructions is actually rather difficult That is not the reason. Its actually far easier to build a fast MISP or RISC-V Out-of-order CPU then it is a x86. Even if you do it for both the MIPS/RISC-V will run with lower energy and less area. If you look at a ISA countsy you will see that MISP on 64 Bit is not that far behind x86 and RISC-V is actually ahead in instruction count specially when including the C extension that is in the standard for the Linux ABI. See: link to this video
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nickikon Hacker News • Mentions

On “Ask HN: Does anyone have something negative to say about RISC-V?”

…or instruction implementations All I have heard is that the people who know about vectors absolutely love the extension. Why is your problem with it? > bad code density That is just plain false. Its actually extremely good, RV32C and RV64C easily beat every other ISA. Even without the 'C' extension the difference to the other ISA are minimal. See: link to this video > The other general point I really dislike is their focus on ISA as if that matters so much compared to uArch. You don't like that the people who are designing an ISA focus on the ISA? That seems an incredible strange argument. It is well known and the RISC-V people often repeat that ISA don't matter much for performance. That's why it make…
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rwmjon Hacker News • Mentions

On “HiFive1 – Arduino RISC-V Dev Board”

Code density is claimed to be similar to x86 and better than ARM with thumb, see the bottom of this slide: link to this video More information on the original design (not quite the final design) of the Compressed extension can be found in the original research paper: link And ... SPARC. Seriously? Register windows were a failed experiment.
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microcolonelon Hacker News • Mentions

On “RISC-V on the Verge of Broad Adoption”

As of early 2016, with the GCC port at that time, RV32GC was as dense as Thumb, and RV64GC was denser than AArch64 and every other major 64-bit ISA, including AMD64. Though RV64G (no C) was in some extreme cases up to 50% larger than AArch64 (due to inlining memcpy and memset, which are a bit larger without compressed instructions), but usually around the same (except MIPS64, which is way larger than the other 64-bit ISAs, probably because of exposed delay slots). 0 There's some indication that density should have increased somewhat since then, but I haven't looked at it myself. 0: link to this video
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