The Mill CPU Architecture - the Belt (2 of 13)

An in-depth presentation on the Mill CPU's 'Belt' architecture, an operand-passing model that replaces general-purpose registers to avoid register renaming.

Please share via this link: MillComputing.com/docs/belt/ 00:00:00  01   The Belt - a new machine model 00:00:37  02   Two architectures 00:03:12  05   Why huge cost in both power and price? 00:04:31  06   Our result - rough numbers 00:06:33  09   33 MIMD operations per cycle peak 00:07:24  10   33 operations per cycle peak ??? Why? 00:09:59  11   33 operations per cycle peak ??? How? 00:11:20  13   The problem - lots of producers and consumers 00:13:05  17   The cost - and performance limit 00:15:34  23   Why renames? 00:18:28  26   What are the temps used for? 00:19:12  27   Split the uses 00:20:33  29   What you really want... 00:20:55  30   We call it the Belt - like a conveyer belt 00:21:50  32   Multiple operation issue 00:21:58  33   Multiple operation retire 00:22:12  34   Belt addressing - temporal addressing 00:23:56  36   Use it or lose it 00:25:18  37   The scratchpad 00:27:12  38   Single operation with multiple results 00:28:24  39   Function calls 00:30:46  40   Belt save/restore 00:33:36  42   Functional unit pipelines - 64 sources vs 450 00:35:00  43   Wide issue 00:35:48  44   Exposed pipeline 00:38:43  47   In-flight over call 00:40:40  49   Interrupts, traps and faults 00:42:16  50   Data forwarding 00:44:31  51   Belt timing 00:45:30  52   Retiring ops of different latencies 00:48:12  54   Belt data location 00:52:16  57   Summary 00:54:32  60   Want more? 00:55:55               Questions 01:26:22               end 01:26:49               fin