u/infinitenothingin r/FPGA • Recommends
On “Servo control using Zynq”
Sure. Lets say you have a 200MHz clock. So, at idle, if your fifo is empty, you just send a 1. Let's say you have a 200MHz clock. When you have a byte (lets say its the letter A that's 01000001 in binary) at your fifo, you send a 0 as your start bit for 200,000,000/115,200 = 1736 cycles. You can just use a counter (add 1 every cycle until you get to 1736) to time how long to send the start bit. Then you send the least significant bit ( 1) for 1736 cycles and so forth until your byte is done. Then you send the end bit.