u/jackschmidt_notradesin r/FPGA • Recommends
Learning to use behavioral sim to debug Verilog - a general inquiry
So I've been running into some difficulty getting some examples (that I've modified) to work, and in posting about it I realize there's some major issues with my code (verilog).
I'd like to learn the proper methods of debugging through simulation as some of you here have suggested. This youtube video (does anyone know why this guy stopped producing? great content if you ask me) was fantastically simple and helped me figure out how to get my code to run in a testbench wrapper- surprisingly, some of the data showing as expected in the logic analyzer...
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I have outputs that are showing up as unknown in the simulation…