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#verilator#verilog#soc

TestDrive Profiling Master : Virtual FPGA Starter Kit

Jeong HyungKi

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Beginner. No background in the topic needed.

1.2K views4 years ago1 recommendation

HardwareSystems programmingFPGAs and digital designEmbedded systems

Jeong HyungKi demonstrates how to simulate a Verilog SoC system using the Virtual FPGA Starter Kit without needing physical hardware.

This is Virtial FPGA Starter Kit. It's a part of TestDrive Profiling Master's some HDL simulation examples for beginners. (I accidentally forgot to set "Simulation Top Design" to "StarterKit/sand_box/top.v" in the properties view. Note please.) By emulating a virtual FPGA with this Starter kit, students or researchers and anyone can simulate verilog SoC system very easily. Home : testdrive-profiling-master.github.io/ Installation guide : testdrive-profiling-master.github.io/wiki/?Installation.md QnA : clonextop@gmail.com If you have any suggestions, please let me know.

Why it's here

1 person recommends this

What people say. Recommended as a useful simulation project for FPGA beginners who do not own physical hardware.

u/Suspicious_Goal_3046in r/FPGA • Recommends

Useful project for FPGA beginners without real FPGA