LaurieWired introduces Tailslayer, a C++ library that reduces DRAM tail latency by using a hedged read strategy.
Modern DRAM is based on a brilliant design from IBM.
But, we're still paying for a latency penalty that's existed since the 60s!
In this video, I'm introducing my personal research project (Tailslayer) that immensely reduces p99.99 latency on traditional RAM!
By implementing a hedged read strategy taking advantage of (undocumented!) channel scrambling offsets, I've gotten as much as 15x reductions in tail latency.
The technique works across Intel, AMD, Graviton, DDR4, DDR5, x86, ARM, you name it.
Check out the C++ lib I wrote, watch the video, and try it yourself!
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Timestamps:
Your RAM goes Blind
A 400ns tRFC Lockout
Can we predict it?
Hedged Reads
The ROB Trap
Multicore Threading FTW!
Memory Controllers Hate You
A Dark Reason (Rowhammer)
Reverse Engineering Channel Scrambling
Where is my Data? (Physically)
Does it actually work?
ARM Graviton...the Black Box
High Frequency Trading
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My project / code (Tailslayer) on GitHub:
github.com/LaurieWired/tailslayer
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Check out my X account for cool Computer Science stuff!
x.com/lauriewired
Why it's here
2 people recommend this
What people say. Recommended as a fascinating deep dive into DRAM latency, channel scrambling, and a software technique to bypass hardware delays.
B
u/BotnicRPMin r/FPGA • Recommends
Great HFT project idea
Hi everybody
Very often on this subreddit, students ask for a good project and often they also mention that they would like to go into HFT (a stupid idea if you ask me, but nobody ever asks me anyways....).
For all those students:
Have a look at this video: [video
I found it very interesting (even though it has nothing to do with FPGA) and I am pretty sure one could do some nice projects with FPGA and PCIe accessing the memory directly. Start being creative!
