Skip to content
0:00 / 0:00

#uvm#systemverilog#easieruvm

Introducing Easier UVM

Doulos Training

8.4K subscribers • 1 video on Hallway

YouTube
  • Recommended by 1 person: 1 in engineering communities.
  • Presented by John Aynsley, co-founder and technical fellow at Doulos
  • Made by the vendor. The company whose product it covers made or sponsored it.

Intermediate. Assumes working knowledge.

21K views11 years ago1 recommendation

HardwareTools and practiceTestingFPGAs and digital design

John Aynsley introduces the Easier UVM coding guidelines and code generator designed to help engineers adopt Universal Verification Methodology quickly.

Doulos co-founder and technical fellow John Aynsley introduces the Easier UVM Coding Guidelines and Code Generator, which you can download from www.doulos.com/easier. Both are open and free to use, and can help you to start using UVM more quickly. This is just one of a series of UVM tutorials, watch the rest of the playlist here: youtube.com/playlist?list=PLBIILfL2t1lnvzw7vF0arlvu36Wj4--D7 Doulos provides scheduled classes online and in-person & delivers on-site team-based training & interactive online learning events worldwide – you can find out the very latest on our website: doulos.com POPULAR UVM TRAINING UVM Adopter Class: bit.ly/43EfsGy Comprehensive SystemVerilog : bit.ly/3qKkKSF To enquire about training for you, or for your team : bit.ly/3WZ9a1W Subscribe to our channel, @DoulosTraining, for more: - Introductory videos to range of our most popular training topics – System Verilog, UVM, SystemC & TLM-2.0, VHDL, Python & Deep Learning, & Arm. - Answers to common questions & “how to’s ”. - Our latest live & on-demand webinars (& joining links). Subscribe (and set your notifications): bit.ly/3MYWzsk Follow us on Twitter: @DoulosTraining Follow us on LinkedIn: uk.linkedin.com/company/doulosltd

Why it's here

1 person recommends this

What people say. Recommended as a helpful resource for design engineers learning Universal Verification Methodology.

Moments people linked to

u/Viper_ACRin r/FPGA • Recommends

On “How to learn UVM as a design engineer?”

As a DV guy going through this right now, I've taken advantage of the Duolos Easy UVM youtube playlist here: https://www.doulos.com/knowhow/systemverilog/uvm/easier-uvm/ [video Also, check out EDA playground, they have an online sandbox simulator you can simulate RTL in: https://www.edaplayground.com you'll need to sign in with an account for free access. Finally I got 2x books: https://www.amazon.com/dp/0615819974?ref=ppx\_yo2ov\_dt\_b\_fed\_asin\_title https://www.amazon.com/UVM-Primer-Step-Step-Introduction/dp/0974164933/?\_encoding=UTF8&pd\_rd\_w=DyWFx&content-id=amzn1.sym.4efc43db-939e-4a80-abaf-50c6a6b8c631%3Aamzn1.symc.5a16118f-86f0-44cd-8e3e-6c5f82df43d0&pf\_rd\_p=4efc43d…
10View on Reddit