John Aynsley introduces the Easier UVM coding guidelines and code generator designed to help engineers adopt Universal Verification Methodology quickly.
Doulos co-founder and technical fellow John Aynsley introduces the Easier UVM Coding Guidelines and Code Generator, which you can download from www.doulos.com/easier. Both are open and free to use, and can help you to start using UVM more quickly.
This is just one of a series of UVM tutorials, watch the rest of the playlist here: youtube.com/playlist?list=PLBIILfL2t1lnvzw7vF0arlvu36Wj4--D7
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u/Viper_ACRin r/FPGA • Recommends
On “How to learn UVM as a design engineer?”
As a DV guy going through this right now, I've taken advantage of the Duolos Easy UVM youtube playlist here: https://www.doulos.com/knowhow/systemverilog/uvm/easier-uvm/
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Also, check out EDA playground, they have an online sandbox simulator you can simulate RTL in: https://www.edaplayground.com you'll need to sign in with an account for free access.
Finally I got 2x books:
https://www.amazon.com/dp/0615819974?ref=ppx\_yo2ov\_dt\_b\_fed\_asin\_title
https://www.amazon.com/UVM-Primer-Step-Step-Introduction/dp/0974164933/?\_encoding=UTF8&pd\_rd\_w=DyWFx&content-id=amzn1.sym.4efc43db-939e-4a80-abaf-50c6a6b8c631%3Aamzn1.symc.5a16118f-86f0-44cd-8e3e-6c5f82df43d0&pf\_rd\_p=4efc43d…