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#verilog#timing-closure#fpga

Fixing failed timing, a practical example in verilog!

FPGAs for Beginners

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YouTube
  • Recommended by 1 person: 1 in engineering communities.
  • Presented by Stacey, creator of FPGAs for Beginners

Intermediate. Assumes working knowledge.

8.9K views5 years ago1 recommendation

HardwareSystems programmingFPGAs and digital designPerformance and optimization

Stacey demonstrates how to resolve timing violations in Verilog by introducing registers and adjusting simulation behavior.

Hi, I'm Stacey, and in this video I fix some timing issues! Buy me a coffee to support my channel: buymeacoffee.com/fpgasforbeginners HDLForBeginners Discord! discord.gg/UTyHa9rG Google form to give me your feedback: forms.gle/ssNwzTKiioj3RNHD9 Ending music: Faith by David van Niekerk youtu.be/JLqvAHdZ1Q4 I'm on discord on the r/fpga server (discord.com/invite/WE7eXCcatY), as Stacey, come say hi and chat all things FPGA! Intro Failed Timing Report Failing Code Adding in a register Simulation behaviour Compensating for extra registers Timing report round 2 Timing report round 3 Outro

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1 person recommends this

What people say. Recommended as a practical, hands-on example of fixing timing issues in FPGA designs.

u/HDLForBeginnersin r/FPGA • Recommends

Fixing failed timing, a practical example in verilog!
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