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Zynq Part 1: Vivado block diagram (no Verilog/VHDL necessary!)

Name: Zynq Part 1: Vivado block diagram (no Verilog/VHDL necessary!)
Uploaded: 2023-07-28T17:00:30Z
Duration: 20 min
Channel: FPGAs for Beginners
Description: Stacey demonstrates how to create a basic Zynq project in Vivado using block diagrams without writing VHDL or Verilog.

FPGAs for Beginners

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Recommended by 1 person: 1 in engineering communities.
Presented by Stacey

Beginner. No background in the topic needed.

75K views3 years ago1 recommendation

Hardware FPGAs and digital design

Stacey demonstrates how to create a basic Zynq project in Vivado using block diagrams without writing VHDL or Verilog.

Hi, I'm Stacey, and in this video I show the vivado side of a basic Zynq project with no VHDL/Verilog required. Not Sponsored, I just use this software a lot! Download vivado here: xilinx.com/support/download.html Buy me a coffee to support my channel: buymeacoffee.com/fpgasforbeginners

Why it's here

1 person recommends this

What people say. Recommended as a beginner-friendly introduction to Zynq and Vivado block diagrams.

u/HDLForBeginnersin r/FPGA • 3 years agoRecommends

It's a Zynq/Vivado example block diagram video!

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