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#pipelining#verilog#timingconstraints

How to fix Timing Errors in your FPGA design during Place and Route, meeting clock constraints

nandland

59K subscribers • 8 videos on Hallway

YouTube
  • Recommended by 2 people: 2 in engineering communities.

Intermediate. Assumes working knowledge.

39K views5 years ago2 recommendations

HardwareSystems programmingFPGAs and digital designPerformance and optimization

Nandland explains how to resolve timing errors in FPGA designs by pipelining combinational logic in Verilog.

Learn how to fix timing errors in your FPGA design. I show a Verilog example that fails to meet timing, then show how to pipeline the code to make it meet timing once again. Breaking up your logic into smaller operations will help lower propagation delay and get your design to run through the Place and Route part of the Synthesis tools correctly. If you like this video and want me to make more, please support me on Patreon: patreon.com/nandland The Go Board is the best FPGA development board for beginners. Get one for yourself today: nandland.com/goboard/introduction.html

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2 people recommend this

What people say. Recommended as a great exercise and clear explanation of how to fix timing constraints using pipelining.

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u/clbrriin r/FPGA • Recommends

Is it possible to pipeline a single instruction? In the Nandland video at [video there is an example where a long sequence of combinational logic, i.e. ```verilog o_Data <= ((r0_Data / 3) + 1) * 5; ``` is optimized to run faster by pipelining it to three stages: ```verilog r1_Data <= r0_Data / 3; r2_Data <= r1_Data + 1; o_Data <= r2_Data * 5; ``` I am running into a performance situation where I just have a single addition, along the lines of: ```verilog input reg 7:0 r0_Data; output reg 7:0 o_Data; ... o_Data <= r0_Data + 1; ``` Is it possible to pipeline this kind of code? I have tried to just write ```verilog r1_Data <= r0_Data + 1; o_Data <= r1_Data; ``` thinking that may…
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u/Suspicious_Piano_Keyin r/FPGA • Recommends

On “how to deal with timing errors? Slow the clock or fix the logic”

I watched a Nandland video about failing timing constraints and pipelining link to this video Watching this I was able to fix my code and pass timing constraints. It’s a great exercise to do. I was/am using the Cu board as well.
2View on Reddit