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#verilog#lutsig#formalverification
Lutsig: A Verified Verilog Compiler for Verified Circuit Development
Andreas Lööw
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- Recommended by 1 person: 1 in engineering communities.
- Presented by Andreas Lööw
- Linked in the descriptionDOI 10.1145/3437992.3439916
Advanced. Deep dive for people who know the field.
302 views5 years ago1 recommendation
HardwareSystems programmingCompilers and interpretersFormal methods and verificationFPGAs and digital design
Andreas Lööw presents Lutsig, a verified Verilog compiler designed for verified circuit development.
Presentation for the paper with the same name, see doi.org/10.1145/3437992.3439916Why it's here
1 person recommends thisWhat people say. Recommended as a presentation on a verified Verilog synthesizer and compiler.